![]() ![]() Altium, Eagle, Cadence, and Mentor Graphics. ![]() Also it may be required to have the Air Gap Width value slightly larger to ensure connection. Plated Half-Holes or Castellated Holes PCB Annular Rings PCB Via-in-Pad PCB Sideplating PCB Hole Drilling PCB Silkscreen. Always utilize the bottom and top edge as the hole’s location. ![]() When designing the castellated holes, there’s a need to take note of the cast hole’s minimum diameter. In this example the Polygon Clearance is 20mils therefore the Polygon Connect Style Rule Conductor Width value is set to 20mils. The castellated hole’s minimum diameter should be around 0.04 inches or 10 mm. Place a small pad for each polygon connection point required.Įnsure that your Clearance Rules set for Polygons matches the Conductor Width of the Polygon Connect Style Rule. To ensure the small pads are connected by spokes, position them close to the edge of the custom shape so that the distance from the small pad edge to the edge of the custom shape is less than half the polygon connection spoke width. The software uses the small pads included in the custom pad shape as the polygon connection points. via diameter 0. via diameter 0.25mm hole clearance 2 oz copper 8mil trace width & clearance 0.3mm min. Design rules 2 layer 1 oz copper 5mil trace with & clearance 0.3mm min. If these pads need to connect to a surrounding polygon, you should consider the polygon thermal connection spokes during the design of the custom pad. JLCPCB design rules and stackups for Altium Designer. How to create thermal connections between polygons and custom padsĬustom pads are often created for components that have larger, unusually shaped pads. You can also disable the display of holes by toggling the for the desired setting (s). How to create Thermal Relief Connections between Polygons and Custom pads. The via hole color is shown in the Via Holes setting in the System Colors section. ![]()
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